类似的网站 Verilog.Net

Information on conference 2003, conference archives, a special interest group and FAQ.

By Simucad. 64-bit Verilog HDL simulation products for FPGA and ASIC design and test. Included are a Verilog HDL Finite State Machine Editor, Waveform Viewer, and ...

a version of Source Navigator that works with Verilog. Provides class and hierarchy views of Verilog designs.

A free perl script that converts verilog to html with most things linked. Also creates hierarchies and indexes for your design.

JHDL is a method of describing (programmatically, in JAVA) the components and connections in a digital logic circuit.

Sutherland HDL training workshops on Verilog and SystemVerilog. Developed and presented by engineering experts. Emphasize on proper usage of HDLs for logic ...

Python package for using Python as a hardware description and verification language.

Book by James M. Lee. Details on the book and a interactive Verilog FAQ.