类似的网站 Rhdl.Rubyforge.Org

JHDL is a method of describing (programmatically, in JAVA) the components and connections in a digital logic circuit.

Describes the department, staff and courses.

Python package for using Python as a hardware description and verification language.

Seeks to design and publish core designs under a license for hardware modelled on the Lesser General Public License (LGPL) for software.

appsy:daisy specializes in developing elegant, functional web applications using the Ruby on Rails framework for rapid development.

VHDL, Verilog, SystemVerilog, SystemC, ARM, Embedded, Xilinx, Altera, Perl, Tcl/Tk, training and consultancy.

Bluespec, Inc. manufactures an ESL synthesis toolset that significantly accelerates hardware design & reduces verification costs.